The present invention relates to a MOS type semiconductor device used with LSI etc., especially, to a semiconductor device using high permittivity material or ferroelectric material as a gate insulation film.
In recent years, by scaling the transistor by the fine processing technology etc. in a semiconductor technological field, several 1,000,000 transistors come to be integrated in one high chip of several cm2, and are used here and there of a mainframe computer, a personal computer, home electric appliances product, a car, and a portable telephone, etc.
In general, when the transistor is reduced, for example, when the size of the transistor is made 1/k by scaling in a constant electric field, the parameter of each transistor is scaled as follows. Where, thickness of the gate oxide film: Tox/k, length of the channel: L/k, channel width: W/k, density of impurities in the Si substrate: NAxc3x97k, junction depth of the source-drain section: Xj/k, and power-supply voltage: Vdd/k.
Thus, the area of the transistor is reduced proportional to reciprocal of square like the following equation.
(W/k)xc3x97(L/k)=WL/k2.
Moreover, a gate load capacity C of the transistor is shown in the following equation.   "AutoLeftMatch"                              C          =                      xe2x80x83                    ⁢                                    ϵ              /                              (                                  Tox                  /                  k                                )                                      xc3x97                                          (                                  W                  /                  k                                )                            /                              (                                  L                  /                  k                                )                                                                                  =                      xe2x80x83                    ⁢                                    {                                                (                                      ϵ                    /                    Tox                                    )                                xc3x97                W                xc3x97                L                            }                        /            k                              
Then, driving current of the transistor is reduced to 1/k like the following equation.
I=xcexc∈/(Tox/k)xc3x97(W/k)/(L/k)xc3x97(Vdd/kxe2x88x92Vt)xc3x97kxcx9c{(xcexc∈/Tox)xc3x97(W/L)xc3x97Vddxe2x88x92Vdd}/k.
Therefore, when the wiring capacity and the wiring resistance are disregarded, an operation delay t of the transistor is reduced like the following equation in proportion to the scaling coefficient k.
t=Q/I={(C/k)xc3x97(Vdd/k)}/(I/k)=t/k
Where, Q shows the charge.
It can be said that today""s LSI can be sped up by scaling the transistor. FIG. 1A shows real size of the transistor which has been achieved in mass production today. This transistor has thickness of the gate oxide film of Tox=5 nm, channel length of L=0.2 xcexcm, and junction depth of the source-drain section of Xj=100 nm.
By the way, it is expected that a big leakage current of the gate oxide film, which flows between the gate electrode and the substrate and between the gate electrode and the source-drain, becomes a trouble, when the transistor will be scaled hereafter toward a previous generation.
In a current gate oxide film, an FN-tunneling current (Fowler-Nordeim-Tunneling) is predominant. Here, the FN-tunneling current increases substantially by the second power of the electric field as the electric field applied to the gate oxide film becomes large by thinning the oxide film. In addition, the tunneling current (Direct-Tunneling) starts to flow directly from the vicinity of Tox=3 nm to 4 nm, when thinning the oxide film. It has a big problem where a greatly large gate current flows compared with the FN-tunneling, since the direct-tunneling current is not only increases in proportion to the electric field but also increases in exponential compared with thinning the gate oxide film.
A following fatal disadvantage is caused by the leakage current of the gate oxide film: 1) The standby leakage current of the entire LSI chip increases. 2) Since the charge accumulated in the gate leaks, a dynamic circuit is not operated. 3) Since the charge accumulated in the cell capacitor such as DRAM leaks, it is not operated as the memory. 4) It is impossible to compare with the turning on current of the transistor when thinning the gate oxide film, and a static circuit itself is not operated.
FIG. 1B shows the size of the transistor after ten years when scaling of the transistor today continues. This transistor has thickness of the gate oxide film of Tox=1.5 nm, channel length of L=50 nm (0.05 xcexcm), and junction depth of the source-drain section of Xj=10 nm.
The gate leakage current increases by the actual measurement as many as eight digits, e.g., from 4xc3x9710xe2x88x9217 A/xcexcm2 to 4xc3x9710xe2x88x929 A/xcexcm2 at Vdd=0.5V, when the thickness of the gate oxide film is changed from Tox=3.5 nm to 1.6 nm. With this, the charge stored by the gate of the transistor of size of, for example, W/L=0.4 xcexcm/0.05 xcexcm and the Tox=1.5 nm is as follows.
0.4 xcexcmxc3x970.05 xcexcmxc3x978.854xc3x9710xe2x88x9214 F/cmxc3x974/1.5 nm=0.5 fF
On the other hand, the gate leakage current is as follows.
0.4 xcexcmxc3x970.05 xcexcmxc3x974xc3x9710xe2x88x929 A/xcexcm2=8xc3x9710xe2x88x9211 A
Therefore, since the time when the charge can be held is only
Q/I=0.5 fF/(8xc3x9710xe2x88x9211 A)=6 xcexcs.
It cannot be used as the memory by all means, when the difference of one digit to two digits is considered, it is impossible to apply to a dynamic circuit. In addition, the leakage current of the entire LSI chip of 1 cm2 square is,
4xc3x9710xe2x88x929 A/xcexcm2xc3x97104 xcexcmxc3x97104 xcexcm=0.4 A.
It becomes an extraordinarily large value as mentioned-above.
On the other hand, in a case of constructing the transistor of L=0.05 xcexcm, by giving up thinning the gate oxide film and setting driving current of the transistor to not so large value, the short channel effect becomes large, thereby it becomes extremely difficult to suppress a DIBL (Drain Induced Barrier Lowering) and a deterioration in S factor. When channel length L is L=0.4{Xjxc3x97Tox(Ws+wd)2}⅓ or less, the short channel effect usually starts to become remarkable. Where, Xj is junction depth of the source-drain section, Tox is a thickness of the gate oxide film, and Ws+Wd is a sum of the width of a depletion layer of the source and the drain. It is necessary to over-scale the junction depth Xj etc. of the source-drain section to a value corresponding to Tox which cannot be reduces.
However, since Xj is still small as about 100 nm today, a lot of difficulties are attended to form a more shallow junction. That is, since an FN-tunneling current and a direct tunneling current increase in exponential to keep using the oxide film to the conventional gate insulation film, there is a disadvantage with a lot of difficulties.
A try which uses the high dielectric film as the gate insulation film as shown in FIG. 2 to solve this disadvantage film, recently. While relative permittivity (∈r) of the gate oxide film such as SiO2 is about four, since the relative permittivity is big such that the relative permittivity is about 7 to 8 in Si3N4 and NO, the relative permittivity is about 20 to 30 in Ta2O5, the relative permittivity is about 80 in TiO2, the relative permittivity is 100 to 200 in SrTiO3, the relative permittivity is 250 to 300 in BaXSr1xe2x88x92xTiO3, the same driving current of the transistor is:
I=xcexc∈O∈r/Toxxc3x97(W/L)xc3x97Vddxc3x97Vdd,
if the material having a large relative permittivity are used as a gate insulation film.
Therefore, the substantial gate insulation film thickness can be thickened to obtain the same driving current, that is, to obtain the gate capacity per the same unit area by conversion of the thickness of the oxide film. For example, in TiO2, it is possible to achieve conversion Tef=1.5 nm of the thickness of the oxide film by a thick film such as film thickness:
T=(80/4)xc3x971.5 nm=30 nm.
However, the following problems exist when the gate insulation film is achieved by the high dielectric film. Since the band gap of the insulation film generally becomes a small value such that material has the larger relative permittivity, as a result, the barrier heights between the gate electrode and the gate insulation film and between the Si substrate and the gate insulation film become small. The small barrier height means that it is easy for electrons to flow in the insulation film by exceeding the barrier height, that is, a lot of leakage currents of gate insulation film flow.
The relationship of the relative permittivity in each insulation film material and the electric field where the insulation destruction is caused is shown in the lower right of FIG. 2. FIG. 2 shows that the electric field of the insulation destruction is almost in inverse proportion to the relative permittivity. That is, even when the electric field applied to the gate insulation film is buffered by using the material with a high relative permittivity and the gate oxide film of the same thickness in oxide film conversion, that is, the gate insulation film with thick only amount corresponding to a largeness of permittivity, this can be said it is equal to the flow of the gate insulation film leakage current equal with the oxide film after all. With this, it is impossible to expect many advantages even if there is an advantage in which the gate leakage current is decreased by using a high permittivity material as a gate insulation film.
Thus, even when the gate insulation film thickness with the oxide film conversion is thinned by using the high dielectric material for the gate insulation film, the electric field of the breakdown voltage lowers since the band gap of the high dielectric material is small, and as the result the difficulty is attended more than the oxide film to thin the gate insulation film thickness of the conversion of the thickness of the oxide film.
When bringing the above-mentioned disadvantage together, with the oxide film used for the conventional gate insulation film, there is a disadvantage that a FN-tunneling current and a direct tunneling current increase in exponential and the difficulty is attended when the transistor is scaled and the oxide film is made a thin film, and the electric field of the breakdown voltage lowers since the band gap of the high dielectric material is small when the gate insulation film thickness of the conversion of the thickness of the oxide film is reduced by using the high dielectric material for the gate insulation film, consequently, the difficulty is attended to reduce the gate insulation film thickness of the conversion of the thickness of the oxide film more than the oxide film. Oppositely, there is a disadvantage that deterioration in drivability improvement of the transistor, the short channel effect increase, and deterioration in the subthreshold characteristic become remarkable when other parts of the transistor are scaled with keeping thicking the gate insulation film thickness to suppress the gate leakage current.
An object of the present invention is to provide a semiconductor device which can effectively perform scaling of the transistor without thinning the gate insulation film thickness and can improve the drivability of the transistor, suppress the short channel effect, and improve the subthreshold characteristic, etc. with suppressing the gate leakage current in the transistor using a high permittivity material or a ferroelectric material of 20 or more of the relative permittivity as the gate insulation film.
Another objects of the present invention is to provide a semiconductor device which can achieve further more high performance by combining with the conventional transistor.
The present invention adopts the following structures to achieve the above-mentioned object.
The semiconductor device of the present invention comprises: a channel of a first conductive type formed on a surface layer of a semiconductor substrate; a source and a drain of a second conductive type formed on both sides of the channel; a gate insulation film with a first relative permittivity formed at least on the channel directly or through a buffer insulation film; a gate electrode formed on the gate insulation film; and a side insulation film formed at least on a side of the gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity, wherein when assuming that an area of the gate insulation film, which is adjacent to the surface layer on a gate electrode side, is S1, and an area thereof, which is adjacent to the surface layer on the channel side, is S2, the area S1 is larger than the area S2. The first permittivity is 20 or more.
Here, preferable manners of the present invention are as follows.
(1) The area S2 is 1.5 times or more as large as the area S1.
(2) A width of the gate insulation film on the channel side is smaller than a width of the gate insulation film on the gate electrode side in a length along a channel width direction of the gate insulation film.
(3) The section shape of the gate insulation film observed from the direction of the source-drain has a shape such that the cross-section becomes small from a gate electrode side toward the channel side, for example, a convex shape, a trapezoid shape or a sector shape. That is, a sectional shape along a direction of the source-drain of the gate insulation film is one of tapered shape, a trapezoid, a sector, and a stair, or a sectional shape along a direction of the source-drain of the gate insulation film from the gate electrode to the predetermined distance is a rectangle, and is one of a tapered shape, a trapezoid, a sector, and a stair on channel side therefrom.
(4) The first gate insulation film is a high dielectric film or a ferroelectric film including a composition or an element of one of Ta2O5, Sr2Ta2O7, TiO2, SrTiO3, BaTiO3, CaTiO3, BaXSr1xe2x88x92XTiO3, PbTiO3, PbZrxTi1xe2x88x92xO3, SrBi2Ta2O9, SrBi2(TaXNb1xe2x88x92x)2O9, or Bi2(TaxNb1xe2x88x92x)O6.
(5) The side insulation film is a low dielectric film which includes the compositions or elements such as SiO2, Si3N4, NO, F added SiO2, CH3-group mixed SiO2, TEOS, polyimide or porous SiO2.
(6) The buffer insulation film includes one of SiO2, Si3N4, NO, TiO2, SrTiO3, MgO or CeO2.
(7) The semiconductor substrate is an SOI substrate in which the semiconductor layer is formed on the monocrystalline semiconductor substrate through the insulation layer.
Though in the gate insulation film which uses a conventional SiO2, high dielectric film, and a ferroelectric film, the method is only in thinning the gate insulation film to improve drivability of the transistor, there is a disadvantage of the gate leakage current.
Area S1, which contacts with (faces) the channel side of the gate insulation film, is small compared with area S2 which contacts with (faces) the gate electrode side thereof according to the semiconductor device of the present invention. As a result, S2 becomes larger than S1 compared with the conventional transistor of S2=S1. Therefore, when the voltage is applied to the gate electrode, since the permittivity of the insulation film which surrounds both sides of the gate insulation film is smaller than that of the gate insulation film, the electric flux of the gate insulation film generated by the charge on the gate electrode side does not direct to the insulation film which surrounds both sides of the gate insulation film too much and the area of the gate insulation film (i.e., length from the direction between source-drain terminals of the transistor) becomes small (short) on the channel side, thereby the above-mentioned electric flux concentrates on the channel side, and as a result the electric flux density becomes large on the channel side compared with the gate insulation film side.
In other word, in the present invention comparing with the conventional ones, when an upper channel length (Defined in the part where the gate electrode and the gate insulation film are contacted) is long, the capacity per the unit channel width of the same lower channel length (Defined in the part where the gate insulation film and the semiconductor substrate which includes the channel, the source, and the drain are contacted) of the gate of the transistor becomes large with the gate insulation film of the same gate insulation film thickness in the same permittivity. As the result, according to the present invention, when the thickness of the gate insulation film is constant, the induced channel charge density becomes large compared with conventional ones. With this advantage, an improvement of drivability of the transistor can be achieved without thinning the gate insulation film thickness with suppressing the gate leakage current.
As described above, according to the present invention, the same advantage in case of thinning the gate insulation film is effected, and the suppression of the short channel effect and the improvement of the subthreshold characteristic can be achieved. Moreover, the width of the gate of the gate electrode along the direction of the source-drain is enlarged, thereby the decrease of the gate wiring resistance becomes possible. Moreover, the electric flux density lowers toward the gate electrode side of the gate insulation film along the direction of the channel-gate electrode. This can be suppressed to decrease the substantial gate insulation film capacity, by the capacity generated with depletion of the gate electrode side generated in the case of using the semiconductors such as n+-polysilicon and p+-polysilicon as a gate electrode material in all the gate electrodes or the parts which contact with the gate insulation film surface side.
It is briefly described that when the gate insulation film is subdivided along the direction of the channel-gate electrode, the capacity of each subdivided gate insulation film becomes a large value directing to the gate insulation film side. That is, capacity with this depletion layer becomes large in the present invention compared with the conventional transistor because of the area increase, and the width of a depletion layer may be reduced.
In the present invention, a shape in the section of the gate insulation film divided in respect along the direction of the source-drain electrode and gate the direction of the electrode-channel can be formed with shapes of the trapezoid whose upper channel width is larger than a lower channel width, the sector in the opposite direction in which the upper channel has roundness, and convex shape in the opposite direction in which the upper channel width is larger than a lower channel width, and is possible to achieve them more easily when film thickness of the gate insulation film is larger than the upper channel width, or when it is comparably large even if it is small. To achieve them, the gate insulation film of high dielectric material and ferroelectric material that relative permittivity is 20 or larger, that is, a high dielectric film or a ferroelectric film which includes the composition or elements such as Ta2O5, Sr2Ta2O7, TiO2, SrTiO3, BaTiO3, CaTiO3, BaxSr1xe2x88x92xTiO3, PbTiO3, PbZrxTi1xe2x88x92xO3, SrBi2Ta2O9, SrBi2(TaxNb1xe2x88x92x)2O9, or Bi2(TaxNb1xe2x88x92x)O6, is preferable.
Moreover, it is preferable to cover both sides of the gate insulation film with the insulation film which includes the composition or elements such as SiO2, Si3N4, NO, F added SiO2, CH3-group mixed SiO2, TEOS, polyimide or porous SiO2 with a comparatively low relative permittivity in order that the electric flux of the gate insulation film directs to the channel, and does not leak to the insulation film side which covers the gate insulation film. In addition, the gate insulation film and the channel of Si may be directly connected, and may place the buffer films such as SiO2, Si3N4, NO, TiO2, SrTiO3, MgO or CeO2.
Moreover, in the conventional art, when applying the same gate voltage, if gate insulation film thickness=T/k (k=S factor greater than 1) for gate insulation film thickness=T, though the applied electric field of the entire gate insulation film increases to kE and k times, the channel surface charge density of the transistor becomes k times, the gate leakage current abruptly increases because of increasing the electric field.
On the other hand, according to the present invention, since the electric flux density increases on the channel side, and the channel surface charge density of the transistor can be k times by designing such as (upper channel length/(lower channel length)=xcex2( greater than 1) with the gate insulation film=T, drivability of the transistor can be improved with a constant film thickness. Though the electric field at this time becomes kE on the channel side as well as the case to make the film thickness T/k, the electric field lowers by directing to the gate electric field side, and becomes Ek/xcex2(k/xcex2 less than 1) oppositely on the gate electrode side, and the electric field becomes small compared with the case of conventional gate insulation film=T.
This result can be understood as follows. That is, certainly, in the present invention, though the electrons are accelerated in electric field kE, exceed the barrier height and flow from the channel side to the gate insulation film side, thereafter the electrons hop the trap in the gate insulation film and reach the gate electrode side. Since the electric field in this part takes a small value, the flowing current is decreased in this hopping conduction according to the present invention.
Another semiconductor devices of the present invention comprises: a channel of a first conductive type formed on a surface layer of a semiconductor substrate; a source and a drain of a second conductive type formed on both sides of the channel; a gate insulation film with a first relative permittivity formed at least on the channel directly or through a buffer insulation film; a gate electrode formed on the gate insulation film; and a side insulation film formed at least on a side of the gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity, wherein an electric flux density in the gate insulation film on the channel side is closer than that on the gate electrode side.
Still another semiconductor devices of the present invention comprises: a plurality of first MOS type transistors each comprising a first channel of a first conductive type formed on a surface layer of a semiconductor substrate, a first source and a first drain of a second conductive type formed to both sides of the first channel, a first gate insulation film with a first relative permittivity formed at least on the first channel directly or through a buffer insulation film, a first gate electrode formed on the first gate insulation film, and a first side insulation film formed at least on side of the first gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity; and a plurality of second MOS type transistors each comprising a second channel of a first conductive type formed on a surface layer of the substrate, a second source and a second drain of a second conductive type formed on both sides of the second channel, a second gate insulation film with the first relative permittivity formed at least on the second channel directly or through a buffer insulation film, a second gate electrode formed on the second gate insulation film, and a second side insulation film formed at least on side of the second gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity, wherein when a cross-section on the first channel side of the first gate insulation film is assumed to be S1, a cross-section on the first gate electrode side is assumed to be S2, a cross-section on the second channel side of the second gate insulation film is assumed to be S3, and a cross-section on the second gate electrode side of the second gate insulation film is assumed to be S4, a condition of: S2/S1 greater than S4/S3 is satisfied. The first permittivity is 20 or more.
Where, a voltage applied to the first gate electrode is lower than a voltage applied to the second gate electrode. Moreover, the structure same as the preferable manner previously described can be applied to another semiconductor device according to the present invention.
In another semiconductor device of the present invention, it is shown that the present invention can be applied and has an advantage even in another case that lower limit of the gate insulation film is not determined by the gate leakage current. For example, in the case with DRAM and the logic-integrated-chip, since Vpp potential which is higher than power-supply voltage Vdd is applied to the memory in DRAM, thick gate insulation film, which can endure the Vpp and keep the reliability of the transistor (deterioration and gate leakage current of the transistor), is necessary as the gate insulation film. However, the gate insulation film is too thick when using this transistor with the DRAM peripheral circuit and the logic section which uses the Vdd power supply as it is, to achieve high-performance DRAM-logic integrated LSI because the performance thereof is inferior compared with the chip which drivability of the transistor manufactured in the process only for logic.
According to the present invention, by using a transistor of (upper portion channel length)/(lower channel length)=xcex2( greater than 1) with a constant gate insulation film thickness as a transistor of the DRAM peripheral circuit and the logic section to which Vdd is applied, drivability of the transistor can be improved. In this case, at least the channel side electric field in which the electric field of the transistor of the Vdd application becomes maximum being the same as the channel side electric field of the transistor of the Vpp application can be raised. This example is an example which reliability is not limited by a gate leakage current of the transistor of the Vdd application.
As mentioned-above in detail, according to the present invention, improvement of drivability of the transistor, suppression of the short channel effect, improvement of the subthreshold characteristic, the decrease of the gate wiring resistance, and the suppression of an increase in the effect gate insulation film thickness by depletion of the gate electrode side, etc. can be achieved, with suppressing the gate leakage current, without thinning the gate insulation film thickness. Moreover, integrated LSI etc. with high-performance can be achieved by combining conventional transistors with the transistor of the present invention.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.